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The most accurate power analysis tools are available for the circuit level but unfortunately, even with switch- rather than device-level modelling, tools at the circuit level have disadvantages like they are either too slow or require too much memory thus inhibiting large chip handling.
The majority of these are simulators like SPICE and have been used by the designers for many years as performance analysis tools.
Due to these disadvantages, gate-level power estimation tools have begun to gain some acceptance where faster, probabilistic techniques have begun to gain a foothold.
But it also has its trade off as speedup is achieved on the cost of accuracy, especially in the presence of correlated signals.
Over the years it has been realized that biggest wins in low power design cannot come from circuit- and gate-level optimizations whereas architecture, system, and algorithm optimizations tend to have the largest impact on power consumption.
Therefore, there has been a shift in the incline of the tool developers towards high-level analysis and optimization tools for power.
It is well known that more significant power reductions are possible if optimizations are made on levels of abstraction, like the architectural and algorithmic level, which are higher than the circuit or gate level [3] This provides the required motivation for the developers to focus on the development of new architectural level power analysis tools.
This in no way implies that lower level tools are unimportant. Instead, each layer of tools provides a foundation upon which the next level can be built.
The abstractions of the estimation techniques at a lower level can be used on a higher level with slight modifications. It is a technique based on the concept of gate equivalents.
The complexity of a chip architecture can be described approximately in terms of gate equivalents where gate equivalent count specifies the average number of reference gates that are required to implement the particular function.
The total power required for the particular function is estimated by multiplying the approximated number of gate equivalents with the average power consumed per gate.
The reference gate can be any gate e. This technique further customizes the power estimation of various functional blocks by having separate power model for logic, memory, and interconnect suggesting a Power Factor Approximation PFA method for individually characterizing an entire library of functional blocks such as multipliers, adders, etc.
The power over the entire chip is approximated by the expression:. Where K i is PFA proportionality constant that characterizes the i th functional element,G i is the measure of hardware complexity, and f i denotes the activation frequency.
G i denoting the hardware complexity of the multiplier is related to the square of the input word length i. N 2 where N is the word length.
The resulting power model for the multiplier on the basis of the above assumptions is:. The figure clearly suggests a flaw in the UWN model.
From Wikipedia, the free encyclopedia. Not to be confused with Register transfer language or Resistor—transistor logic.
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